Programmable logic devices (PLDs) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), transceivers, and so forth.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an internal memory or an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. In some CPLDs, configuration data is stored on-chip in non-volatile memory. In other CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration sequence.
For all of these programmable logic devices (PLDs), the functionality of the device is controlled by data bits provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, e.g., using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable.
ICs use various sorts of devices to create logic circuits. Many types of ICs use complementary metal-oxide-semiconductor (“CMOS”) logic circuits. CMOS logic circuits use CMOS cells that have a first-conductivity-type metal-oxide-semiconductor (“MOS”) transistor (e.g., a p-type MOS (“PMOS”) transistor) paired with a second-conductivity-type MOS transistor (e.g., an n-type MOS (“NMOS”) transistor). CMOS cells can hold a logic state while drawing only very small amounts of current.
It is generally desirable that MOS transistors, whether used in a CMOS cell or used individually, provide good conductivity between the source and the drain of the MOS transistor when operating voltage is applied to the gate of the MOS transistor. In other words, it is desirable that current flows through the channel between the source and the drain when the MOS transistor is turned on.
The amount of current flowing through the channel of an MOS transistor is proportional to the mobility of charge carriers in the channel. Increasing the mobility of the charge carriers increases the amount of current that flows at a given gate voltage. Higher current flow through the channel allows the MOS transistor to operate faster. One of the ways to increase carrier mobility in the channel of a MOS transistor is to produce strain in the channel.
There are several ways to create strain in the channel region. One approach is to deposit stressed layers over a MOS transistor. Another approach is to modify existing structures, such as by implanting ions into the drain and source regions. Yet another approach is to grow stressed material in a recess of the source and/or drain region of a MOS transistor.
FIG. 1 is a simplified cross section of a prior art MOS transistor 100 having stressed material 102 in the source 104 and drain 106 regions. The MOS transistor 100 is a PMOS transistor formed on a silicon substrate 108, and the stressed material is silicon-germanium (“SiGe”) that has been grown in recesses that were previously etched in the silicon. The SiGe has a compressive stress that strains the channel region 110. However, the edges 112 of the SiGe regions are relatively far from the channel region 110, reducing their effectiveness at producing the desired strain in the channel region. The edge 112 can be pushed towards channel by forming undercut during etch, but it is hard to control and difficult to monitor the final amount of undercutting.
Other elements of the PMOS transistor 100 include a gate 114, gate spacers 116, 118, 120, 122, gate dielectric 124, source/drain extension regions 126, and halo implant regions 128.
Another prior art PMOS device uses thin gate offset spacers to define the edges of recesses etched in the source/drain regions. The recesses are then filled with SiGe. In this case, the depth of source/drain area recess is limited by the width of offset spacer due to short channel effect.
Therefore, techniques for producing strain in a channel region of a MOS transistor that avoid the disadvantages of the prior art are desired. Greater control over the amount of strain produced in the channel region is further desirable.